Senior Memory Electrical Validation Engineer at Astera Labs

San Jose, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

AI, Semiconductors, Networking, StorageIndustries

Requirements

Strong academic and technical background in Electrical or Computer Engineering (Bachelor’s minimum, Master’s preferred)
≥5 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications
Professional attitude with ability to prioritize dynamic tasks, plan for meetings, and work with minimal supervision
Entrepreneurial, open-minded behavior and can-do attitude with customer focus
Proven track record solving problems independently, preferably as a tech lead
Familiarity with DDR memory standards and experience in system testing, characterization, margin analysis, and optimization
Working knowledge of key high-speed design blocks such as PLL’s, DFE, Tx EQ
Strong Python scripting ability: object-oriented programming and basic dev ops using git
Deep background in developing bench automation techniques using Python, emphasizing execution efficiency, repeatability, and data analysis
Proficiency using high-speed lab equipment such as BERT, Oscilloscope, and VNA

Responsibilities

Develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions
Formulate a comprehensive post-Silicon validation plan
Automate testing of ICs and board products
Design experiments to root-cause unexpected behavior
Report results and specification compliance
Work with key internal customers to quantify margins and ensure robustness
Certify product’s parametric conformance to customer requirements

Skills

Key technologies and capabilities for this role

Post-Silicon ValidationElectrical ValidationSoC ValidationAutomation TestingRoot-Cause AnalysisCXLPCIeEthernetUALinkServer ApplicationsStorage ApplicationsNetworking Applications

Questions & Answers

Common questions about this position

What education is required for the Senior Memory Electrical Validation Engineer role?

A Bachelor’s degree in Electrical or Computer Engineering is required at minimum, with a Master’s preferred.

What are the key required experiences for this position?

Candidates need ≥5 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications, familiarity with DDR memory standards and system testing, working knowledge of high-speed design blocks like PLL’s, DFE, Tx EQ, strong Python scripting, bench automation techniques, and proficiency with high-speed lab equipment such as BERT, Oscilloscope, and VNA.

What is the salary or compensation for this role?

This information is not specified in the job description.

Is this position remote or does it require office work?

This information is not specified in the job description.

What does Astera Labs look for in a strong candidate?

Astera Labs seeks candidates with a professional attitude to prioritize tasks and work independently, an entrepreneurial open-mind and can-do attitude with the customer in mind, and a proven track record solving problems independently, preferably as a tech lead.

Astera Labs

Semiconductor connectivity solutions for AI infrastructure

About Astera Labs

Astera Labs provides semiconductor-based connectivity solutions aimed at improving the performance of cloud and artificial intelligence (AI) infrastructure. Their products, which include PCIe, CXL, and Ethernet solutions, are designed to facilitate high-speed data transfer, addressing the 'memory wall' issue that can limit computing performance. The company serves clients in the growing cloud AI market, including data centers and businesses that depend on AI and cloud applications. Unlike many competitors, Astera Labs has been recognized for its contributions to the semiconductor industry, being a finalist for the Global Semiconductor Alliance's Most Respected Private Semiconductor Company award. The goal of Astera Labs is to enhance the efficiency and speed of data transfer in modern computing environments, positioning itself as a leader in the semiconductor sector.

Santa Clara, CaliforniaHeadquarters

2017Year Founded

$200.8MTotal Funding

IPOCompany Stage

Data & Analytics, Hardware, AI & Machine LearningIndustries

201-500Employees

Risks

Rapid office expansion could lead to financial strain if growth in demand falters.

Foray into biotechnology may divert resources from core semiconductor business.

Reliance on Nvidia partnership poses risk if strategic focus shifts or partnership disrupts.

Differentiation

Astera Labs offers the industry's first PCIe 6 switch, Scorpio, for AI infrastructure.

The company focuses on overcoming the 'memory wall' in high-speed data transfer solutions.

Astera Labs integrates AI with biotechnology, diversifying beyond traditional semiconductor applications.

Upsides

Astera Labs' relocation to San Jose triples its operational capacity and talent acquisition.

Strategic partnership with Nvidia enhances Astera Labs' credibility in AI and semiconductor markets.

Recent investments from major financial entities indicate strong investor confidence in growth.

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