Senior ASIC Physical Design and Timing Engineer at NVIDIA

This information is not specified in the job description.

This information is not specified in the job description.

Required skills include hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence; expertise in analysis and fixing of timing paths through ECOs including crosstalk and noise analysis; expertise in physical design and optimization like placement, routing, cell sizing, buffering, and logic restructuring; background in logic synthesis and equivalence checking; proficiency in programming and scripting languages such as Perl, Tcl, Python; and in-depth knowledge of industry standard EDA tools.

NVIDIA is described as a dynamic and growing team that is a 'learning machine' constantly evolving by adapting to new opportunities which are hard to tackle, that only they can pursue, and that matter to the world, with a focus on amplifying human inventiveness and intelligence in a cross-functional environment.

Candidates can stand out with background in domain specific STA and timing convergence such as CPUs, GPUs or Network processor implementation or SOCs; understanding of DFT logic and experience with DFT timing closure for various modes; and knowledge of deep sub-micron technologies.