Sr. ASIC Design Verification Engineer
GroqSalary not specified
Full Time
Senior (5 to 8 years)
$161,300 – $260,000Compensation
Senior (5 to 8 years), Expert & Leadership (9+ years)Experience Level
Full TimeJob Type
UnknownVisa
AI, SemiconductorsIndustries
Requirements
- BS in Electrical Engineering, Computer Science, or related field with 15+ years of industry experience or MS in Electrical Engineering, Computer Science, or related field (preferred) with 12+ years of industry experience
- Experience in SoC verification cycle from architecture to tape out to bring up
- Good knowledge of verification methodologies such as UVM/OVM etc
- Hands-on ASIC-SoC Design verification tests and debug experience
- Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology
- Good problem-solving skills
- Passionate about AI and thriving in a fast-paced and dynamic startup culture
- Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM)
Responsibilities
- Work on a path breaking architecture with a highly experienced team
- Contribute to the creation and implementation of multiple SoC verification environments and tape out efforts
Skills
Key technologies and capabilities for this role
Questions & Answers
Common questions about this position
What is the salary range for the Design Verification Engineer, Principal position?
The salary range is $161.3K - $260K.
Is this role remote or hybrid, and what are the location requirements?
This is a hybrid role requiring onsite presence at the Santa Clara, CA headquarters 3 days per week.
What key skills and experience are required for this position?
Required experience includes 15+ years with a BS or 12+ years with an MS in EE/CS, SoC verification from architecture to tape out, UVM/OVM methodologies, hands-on ASIC-SoC verification, and fluency in SystemVerilog randomization, coverage, and assertions.
What is the company culture like at d-Matrix?
d-Matrix values humility, direct communication, inclusivity, transparency, and intellectual honesty, fostering an environment where everyone feels welcomed and empowered.
What makes a strong candidate for this Design Verification Engineer role?
Strong candidates have advanced degrees in EE/CS with extensive industry experience, deep expertise in SoC verification methodologies like UVM, SystemVerilog proficiency, strong problem-solving skills, and passion for AI in a fast-paced startup environment.
d-Matrix
AI compute platform for datacenters
About d-Matrix
d-Matrix focuses on improving the efficiency of AI computing for large datacenter customers. Its main product is the digital in-memory compute (DIMC) engine, which combines computing capabilities directly within programmable memory. This design helps reduce power consumption and enhances data processing speed while ensuring accuracy. d-Matrix differentiates itself from competitors by offering a modular and scalable approach, utilizing low-power chiplets that can be tailored for different applications. The company's goal is to provide high-performance, energy-efficient AI inference solutions to large-scale datacenter operators.
Santa Clara, CaliforniaHeadquarters
2019Year Founded
$149.8MTotal Funding
SERIES_BCompany Stage
Enterprise Software, AI & Machine LearningIndustries
201-500Employees