Design Verification Engineer at Baidu USA

Sunnyvale, California, United States

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

Minimum 5 years of experience in UVM-based verification on a significantly complex project
Advanced knowledge of standard ASIC design and verification flows, simulation, and testbench development
Advanced knowledge of System Verilog and the UVM methodology
Solid verification skills in problem-solving, constrained random testing, coverage closure, gate-level simulations, and X propagation
Proficiency in one scripting language (Perl, Python, or Tcl)
SoC and IP verification experience on PCIe, Ethernet, HBM, GDDR, DDR, MMU, or Cache
Familiarity with C/C++
Experience with Formal Verification (Model Checking, Equivalence Checking)
Excellent communication skills in both English and Chinese

Responsibilities

Develop UVM Testbenches
Generate directed/constrained random test
Perform failure analysis and resolution
Analyze coverage and close coverage gaps
Run RTL and gate-level functional verification
Debug failures and lead bug tracking
Work closely with design and systems engineering teams to review specifications and architecture, extract features, define verification plans, and establish coverage models
Support mixed-signal co-simulation using Verilog models of analog IP
Develop testbenches, test cases, reference models, coverage models, and automate regression suites
Support emulation and silicon bring-up debug, utilizing smart ideas to duplicate problems in simulation

Skills

Key technologies and capabilities for this role

SystemVerilogUVMPerlPythonTclPCIeEthernetHBMGDDRDDRMMUCacheC++Formal VerificationModel CheckingEquivalence CheckingConstrained Random TestingCoverage Closure

Questions & Answers

Common questions about this position

Is this position remote or onsite?

This is an onsite position at Baidu’s Sunnyvale office.

What is the salary for this Design Verification Engineer role?

This information is not specified in the job description.

What key skills are required for this role?

The role requires minimum 5 years of UVM-based verification experience, advanced knowledge of System Verilog and UVM methodology, solid verification skills including constrained random testing and coverage closure, proficiency in one scripting language like Perl, Python, or Tcl, and SoC/IP verification experience with protocols like PCIe or DDR.

What is the company culture like for this team?

The team thrives in small, fast-moving environments, values self-directed individuals who are driven, eager to learn, and team-oriented, with a focus on accomplishing great missions collaboratively.

What makes a strong candidate for this position?

Strong candidates have 5+ years in UVM verification on complex projects, advanced System Verilog/UVM skills, experience with SoC protocols like PCIe or DDR, scripting proficiency, and excellent communication in English and Chinese.

Baidu USA

Culturally tailored search technology provider

About Baidu USA

Baidu's main product is an intelligent, culturally tailored search technology that powers various community-based and vertical search-based products, including web search, Baidu PostBar, Baidu Knows, Baidu Encyclopedia, Maps, Image Search, Video Search, and News Search. Their cutting-edge Box Computing Open Platform provides deep-linked content and applications directly through the search box, demonstrating their commitment to continually innovating to enhance user experience.

3822+XCF, Shang Di Shi Jie, Hai Dian Qu, Bei Jing Shi, China, 100193Headquarters

2000Year Founded

$8,590.8MTotal Funding

EARLY_STAGE_VCCompany Stage

Data & AnalyticsIndustries

10,001+Employees