Performance Modeling Engineer
GroqFull Time
Expert & Leadership (9+ years)
Key technologies and capabilities for this role
Common questions about this position
The role requires strong C++ and SystemC coding skills for developing TLM2.0 performance models, testbenches, and workloads. Knowledge of data movement within modern SoC architectures including interconnect, DDR, PCIe, Ethernet, and embedded processors is essential, along with knowledge of state-of-the-art performance modeling methods. A Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field is required, and FPGA knowledge is a plus.
The primary location is Bengaluru, Karnataka, India.
The role is within the Architecture team and involves close collaboration with fellow architects and designers, as well as cross-team and functional collaboration.
This is a full-time regular position on Shift 1 (India).
Candidates with strong C++ and SystemC skills for TLM2.0 modeling, deep knowledge of SoC data movement and interconnects, and experience in performance modeling tied to real product outcomes will stand out. FPGA knowledge, while a plus, is not essential, and advanced degrees in relevant fields are required.
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