Senior C/C++ Low Latency Engineer at d-Matrix

Zug, Zug, Switzerland

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Not SpecifiedCompensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Finance, TradingIndustries

Requirements

Extensive and thorough knowledge of C and C++ in Linux
Understanding of – and the ability to verify - the assembly the compiler will produce from the code you write
Understanding what (GNU/Linux) system calls you invoke will do and cost
Knowledge of x64 hardware and how to use it efficiently
Understanding what storage structures to select or implement given their use (time complexity)
Ability to work with debuggers and profilers
Operative coding (git, documentation)
Ability to absorb from and provide knowledge to the team
Pro-active, a self-starter, honest, flexible and stress resistant

Responsibilities

Building, testing, monitoring and maintaining large scale parallel applications and databases
Writing low-latency networking code for fast communication with exchanges
Designing and implementing context-switch-free code
Designing and implementing custom data storage structures with minimalistic footprint
Developing data pipelines using a streaming paradigm
Implementing complex trading logic for the decision engine with the lowest possible compute time
Reimplementing existing code using advanced features of the CPU (SIMD)
Optimizing code for performance in data processing pipelines
Improving maintainability and manageability of large, highly optimized and multithreaded codebases while preserving low latency
Building and maintaining global (hardware) infrastructure, including hardware compositions, network design, and data logging pipelines for traders and quants
Involvement in all aspects of the pipeline and different tech stacks

Skills

C++

Low Latency

Networking

SIMD

Multithreading

Parallel Applications

Databases

Data Pipelines

Streaming

Trading Logic

Hardware Infrastructure

Network Design

d-Matrix

AI compute platform for datacenters

About d-Matrix

d-Matrix focuses on improving the efficiency of AI computing for large datacenter customers. Its main product is the digital in-memory compute (DIMC) engine, which combines computing capabilities directly within programmable memory. This design helps reduce power consumption and enhances data processing speed while ensuring accuracy. d-Matrix differentiates itself from competitors by offering a modular and scalable approach, utilizing low-power chiplets that can be tailored for different applications. The company's goal is to provide high-performance, energy-efficient AI inference solutions to large-scale datacenter operators.

Santa Clara, CaliforniaHeadquarters

2019Year Founded

$149.8MTotal Funding

SERIES_BCompany Stage

Enterprise Software, AI & Machine LearningIndustries

201-500Employees

Benefits

Hybrid Work Options

Risks

Competition from Nvidia, AMD, and Intel may pressure d-Matrix's market share.

Complex AI chip design could lead to delays or increased production costs.

Rapid AI innovation may render d-Matrix's technology obsolete if not updated.

Differentiation

d-Matrix's DIMC engine integrates compute into memory, enhancing efficiency and accuracy.

The company offers scalable AI solutions through modular, low-power chiplets.

d-Matrix focuses on brain-inspired AI compute engines for diverse inferencing workloads.

Upsides

Growing demand for energy-efficient AI solutions boosts d-Matrix's low-power chiplets appeal.

Partnerships with companies like Microsoft could lead to strategic alliances.

Increasing adoption of modular AI hardware in data centers benefits d-Matrix's offerings.

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