Sr. ASIC Design Verification Engineer
GroqSalary not specified
Full Time
Senior (5 to 8 years)
Senior ASIC Verification Engineer at Parallel Wireless
Milpitas, California, United States
$130,000 – $175,000Compensation
Senior (5 to 8 years)Experience Level
Full TimeJob Type
UnknownVisa
Telecommunications, SemiconductorsIndustries
Requirements
- BSEE required / MSEE preferred
- 5-12 years of related Verification experience
- Strong knowledge of UVM
- Proficiency with at least one of: C++, Object Oriented Programming, System Verilog
- Strong knowledge of basic concepts of VLSI, SoC architecture
- Ethernet and packet processing experience
- Exceptional analytical skills and problem-solving skills
Responsibilities
- Work with DSP, system, and software engineers to define verification strategies and execute plans at system or full chip level
- Build and continuously improve verification infrastructure and methodologies to meet the demands of next generation SoCs
- Work with system architects, RTL designers, FPGA and emulation engineers to ensure that verification requirements and coverage are met for each project
Skills
UVM
SystemVerilog
C++
Python
VLSI
SoC
Ethernet
packet processing
OOP
Parallel Wireless
Provides 5G wireless infrastructure solutions
About Parallel Wireless
Parallel Wireless provides wireless infrastructure solutions focused on the 5G market, utilizing OpenRAN technology to create open and interoperable mobile networks. Their products help clients like mobile network operators and governments reduce the complexity and cost of deploying and maintaining wireless networks. By offering both hardware and software components, Parallel Wireless enables flexible and scalable network designs that can adapt to changing demands. The company's goal is to lead the telecommunications industry towards more accessible and affordable 5G solutions.
Nashua, New HampshireHeadquarters
2012Year Founded
$1.8MTotal Funding
CONVERTIBLECompany Stage
Hardware, Enterprise SoftwareIndustries
501-1,000Employees