Design Verification Engineer - SoC at Etched.ai

San Jose, California, United States

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$150,000 – $275,000Compensation

Senior (5 to 8 years)Experience Level

Full TimeJob Type

UnknownVisa

Semiconductors, Artificial IntelligenceIndustries

Requirements

Strong understanding of digital design, RTL, and ASIC design flows
Hands-on experience with performance verification, simulation, and modeling
Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog
Skilled in writing Python scripts for automation, data analysis, and performance modeling
Experience building and maintaining performance models for chip subsystems
Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators
Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning
Some exposure to kernel level performance metrics and profiling tools

Responsibilities

Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon)
Work closely with software and application developers on identifying performance bottlenecks and tuning the software
Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification
Improve and maintain the architectural performance models
Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model
Develop SystemVerilog or Python-based checkers for verifying the performance features
Develop coverage monitors and analyze coverage to ensure all performance features are covered
Debug performance issues and conduct performance tuning on silicon
Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle

Skills

Key technologies and capabilities for this role

SystemVerilogPythonRTLASIC VerificationPerformance ModelingCoverage AnalysisTest PlansDebuggingDMA EnginesNoCSystolic Arrays

Questions & Answers

Common questions about this position

What is the salary range for the Design Verification Engineer position?

The salary range is $150K - $275K.

Is this role remote or onsite?

The position is onsite.

What key skills are required for this Design Verification Engineer role?

Required skills include ASIC/SoC design and verification experience, strong SystemVerilog and Python expertise for developing checkers, coverage monitors, and testbenches, and knowledge of architecture and performance modeling.

What does the company culture or team environment look like at Etched?

The role involves close collaboration with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack.

What makes a strong candidate for this DV Engineer role?

Strong candidates have hands-on ASIC/SoC verification experience, expertise in SystemVerilog and Python for testbenches and performance modeling, and familiarity with software performance profiling and bottleneck analysis.

Etched.ai

Develops servers for transformer inference

About Etched.ai

The company specializes in developing powerful servers for transformer inference, utilizing transformer architecture integrated into their chips to achieve highly efficient and advanced technology. The main technologies used in the product are transformer architecture and advanced chip integration.

Cupertino, CA, USAHeadquarters

2022Year Founded

$5.4MTotal Funding

SEEDCompany Stage

HardwareIndustries

11-50Employees